SEBP12-2/2/5/2

GRAPHICS-CLASS PCI EXPRESS BACKPLANE
Core's SEBP12-2/2/5/2 is a graphics-class backplane that supports a x16 PCI Express (PCIe) link from a graphics-class PICMG 1.3 compatible System Host Board to the backplane's PCIE2 slot. High-end PCI Express video and graphics cards are supported with this x16 PCIe electrical link. Core's CEPD or CEP4 are examples of graphics-class PICMG 1.3 SHBs and with an CE-00031 installed these SHB's can provide a x1 PCIe link via the expansion slot to the backplane's PCIE1 slot.

SHB SLOT
Accepts an SHB Express (PICMG® 1.3) compliant (graphics-class) processor such as Core's current CEPD and CEP4 system host boards.

PCI EXPRESS SERIAL SLOTS
PCIE2 is a x16 slot connected to the SHB with a x16 PCI Express link. PCIE1 is a x8 mechanical slot driven by a x1 PCI Express link from the PCIeS expansion slot. In order to use the PCIE1 slot a Core CE-00031 I/O expansion board must be used on Core's CEPD or CEP4 system host board. The CE-00031 enables communication between the SHB/CE-00031 and the PCI Express option card in slot PCIE1.

OPTIONAL USB 2.0 INTERFACES
The SHB Express specification defines optional I/O routings from the SHB to the backplane. Core's SEBP12-2/2/5/2 takes advantage of this new specification feature by providing two USB 2.0 headers capable of providing up to four USB 2.0 backplane ports. Each Core CEPD/CEP4 System Host Board supports two USB port connections to a backplane. A factory installed option provides two additional USB port connections. Contact Core if you are interested in this optional CEPD/CEP4 functionality.

OPTIONAL ETHERNET INTERFACES
Core's SEBP12-2/2/5/2 backplane supports the optional Ethernet routing feature of the SHB Express (PICMG 1.3) specification. Two 10/100/1000Base-T Ethernet RJ-45 connectors are available for use on the backplane. Data communication performance of the backplane's Ethernet interfaces depends on the Ethernet controller hardware and configuration on the system host board. Consult your SHB Ethernet interface implementation method for details. The SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE explains the backplane I/O capabilities supported by Core's PICMG 1.3 System Host Boards.

POWER CONNECTORS
The SEBP12-2/2/5/2 backplane is available with a power connector suitable for use with either an ATX or EPS power supply.

EXTENDED-CURRENT TERMINAL BLOCKS
Three extended-current terminal blocks provide additional power capacity for power-intensive applications -- up to 80 Amps of +12V, 120 Amps of +3.3V and 80 Amps of +5V.

POWER INDICATORS
Surface-mount LEDs provide a convenient visual check for +5V, -5V, +5V AUX,+12V, -12V and +3.3V power connection and status. CAUTION: Never install or remove the SHB or any option card from the SEBP12-2/2/5/2 backplane if the +5V AUX LED is GREEN. If the system appears to be off and the+5V AUX LED is GREEN then you need to remove or turn-off the incoming power to the system power supply.

AUXILIARY POWER CONNECTOR
The +12V power connector on the SEBP12-2/2/5/2 routes auxiliary power to the SHB's edge connectors. This new capability of PICMG 1.3 compliant SHBs and backplanes eliminates the need for auxiliary power connections on the system host board.

PRINTED CIRCUIT LAYERS
The backplane is a six-layer, .080" thick board with three separate signal layers: +5V/+12V, +3.3V and ground. Multi-layer backplane construction provides excellent noise immunity.

PCI-X PARALLEL BUS SLOTS
The five PCI-X slots on the SEBP12-2/2/5/2 are connected to the SHB via a x4 PCI Express link that drives a PCI Express-to-PCI-X bridge chip. The bridge chip provides a 64-bit/66MHz PCI-X channel to support slots A1 through A4 and a 64-bit/133MHz PCI-X channel that supports slot B1. PCI-X and universal (i.e. 5V/3.3V combo or 3.3V only) PCI option cards may be used and the bridge chips will throttle-down the bus interface speeds to match any universal PCI or PCI-X card with an interface bus speed less than 66MHz or 133MHz.

PCI AND ISA PARALLEL BUS SLOTS
The SEBP12-2/2/5/2 supports the optional SHB edge connector D. Edge connector D provides a 32-bit/33MHz PCI interface to drive slots SLTC1 and SLTC2. This PCI Interface also connects to a PCI-to-ISA bridge chip to support ISA slots SLTD1 and SLTD2. Since the ISA bus interface is not part of the PICMG 1.3 specification, it was necessary to make use of a reserve pin from SHB edge connector A and B in order to route the ISA signals NOGO_ISA and SERIRQ from the PICMG 1.3 SHB through these reserve pins and over to the backplane's PCI-to-ISA bridge chip. As a result, if a third party SHB does not support this necessary ISA signal routing, then the SEBP12-2/2/5/2 backplane's ISA card slots will not function. Many of Core's graphics-class SHBs support this necessary ISA bus signal routing. Legacy PCI card support is not impacted by this ISA bus signal routing requirement. The SEBP12-2/2/5/2 backplane slots provide legacy ISA and PCI card support in order to provide a simple and cost effective transition to the PCI Express architecture.

CONNECTING POWER
The combination of new power supply technologies, soft-power control signals available via the Advanced Configuration and Power Interface (ACPI) now supported by PICMG 1.3 SHBs and auxiliary power connectors on PICMG 1.3 backplanes that deliver all of the SHBs power to the edge connectors are requiring a different approach to connecting system power.

Auxiliary power connectors on the backplane are provided to help improve system Mean Time To Repair (MTTR). All power can be delivered to the SHB via the board's edge connectors. Core's PICMG 1.3 SHBs and backplane SHB edge connector slots have ample power pins available to meet the power demands of high-performance, performance-based processor SHBs like the Core CEP4. The ATX/EPS and +12V power connectors on the SEBP12-2/2/5/2 backplane also have an ample number of power pins available to meet these demands. The system designer needs to be aware of the potential power demands of the entire system including the particular SHB to ensure that both the power supply and the power connectors in the cable harness can safely deliver the necessary power to drive the entire system.

Specific implementations of ACPI signals, ATX/EPS power supply type and the operating system software will determine the specific connection method for the power supply. ACPI signal usage is optional and may be turned off using the SHBs BIOS and/or signal jumpers. Specific power connections and BIOS parameters will differ according to unique system design requirements.