SEBP13-4/6/2

GRAPHICS-CLASS PCI EXPRESS BACKPLANE
Core's SEBP13-4/6/2 is a graphics-class backplane that supports a x16 PCIe link from a graphics-class PICMG 1.3 system host board (SHB) to the backplane's PCI Express slot PCIe2. The PCI Express slot labeled PCIe1 is supported by a x1 link from a Core CE-00031 expansion board. A graphics-class SHB provides an additional x4 link that drives a PCI Express-to-Dual PCI-X bridge chip. Connector D on a graphics-class SHB provides an additional 32-bit/33MHz PCI interface to the SEBP13-4/6/2.

SHB SLOT
Accepts an SHB Express (PICMG® 1.3) compliant (graphics-class) processor such as Core's current CECD and CEP4 system host boards.

PCI EXPRESS SERIAL SLOTS
PCIe2 is a x16 mechanical slot connected to the SHB with a x16 PCI Express link. PCIe1 is a x8 mechanical and a x4 electrical slot driven by a x1 PCI Express link from the PCIeS expansion slot. In order to use the PCIe1 slot, a Core CE-00031 I/O expansion board must be used on the graphics-class system host board. The CE-00031 enables communication between the SHB/CE-00031 and the PCI Express option card in slot PCIe1.

PCI-X PARALLEL BUS SLOTS
The six PCI-X slots on the SEBP13-4/6/2 are connected to the SHB via a x4 PCI Express link that drives the PCI Express-to-PCI-X bridge chip. The bridge chip provides one 64-bit/100MHz PCI-X channel that support slots B1 and B2 plus an additional 64-bit/66MHz PCI-X channel that supports slots A1 through A4. PCI-X and universal (i.e. 5V/3.3V combo or 3.3V only) PCI option cards may be used and the bridge chip will throttle-down the bus interface speeds to match any universal PCI or PCI-X card with an interface bus speed less than 100MHz or 66MHz. Slots C1 through C4 support 5V only or universal 32-bit/33MHz PCI cards and are driven by connector D of the SHB.

OPTIONAL USB 2.0 INTERFACES
The SHB Express specification defines optional I/O routings from the SHB to the backplane. Core's SEBP13-4/6/2 takes advantage of this new specification feature by providing two USB 2.0 headers capable of providing up to four USB 2.0 backplane ports. Graphics-class system host board support for the USB port connections to a backplane is optional. Refer to the SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE below for an explanation of the backplane I/O capabilities supported by Core's PICMG 1.3 graphics-class SHBs or contact Core for additional information and SHB product updates.

OPTIONAL ETHERNET INTERFACES
Core's SEBP13-4/6/2 backplane supports the optional Ethernet routing feature of the SHB Express (PICMG 1.3) specification. Two 10/100/1000Base-T Ethernet RJ-45 connectors are available for use on the backplane. Data communication performance of the backplane's Ethernet interfaces depends on the Ethernet controller hardware and configuration on the system host board. Consult your SHB Ethernet interface implementation method for details. The SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE explains the backplane I/O capabilities supported by Core's PICMG 1.3 System Host Boards.

POWER CONNECTORS
The SEBP13-4/6/2 backplane is available with power connectors suitable for use with either an ATX or EPS power supply.

EXTENDED-CURRENT TERMINAL BLOCKS
Two extended-current terminal blocks provide additional power capacity for power-intensive applications -- up to 80 Amps of +12V, 80 Amps of +3.3V and 40 Amps of +5V.

POWER INDICATORS
Surface-mount LEDs provide a convenient visual check for +5V, -5V, +5V AUX,+12V, -12V and +3.3V power connection and status. CAUTION: Never install or remove the SHB or any option card from the SEBP13-4/6/2 backplane if the +5V AUX LED is GREEN. If the system appears to be off and the+5V AUX LED is GREEN then you need to remove or turn-off the incoming power to the system power supply.

AUXILIARY POWER CONNECTOR
The +12V power connector on the SEBP13-4/6/2 routes auxiliary power to the SHB's edge connectors. This new capability of PICMG 1.3 compliant SHBs and backplanes eliminates the need for auxiliary power connections on the system host board.

PRINTED CIRCUIT LAYERS
The backplane is a six-layer, .080" thick board with three separate signal layers: +5V/+12V, +3.3V and ground. Multi-layer backplane construction provides excellent noise immunity.

CONNECTING POWER
The combination of new power supply technologies, soft-power control signals available via the Advanced Configuration and Power Interface (ACPI) now supported by PICMG 1.3 SHBs and auxiliary power connectors on PICMG 1.3 backplanes that deliver all of the SHBs power to the edge connectors are requiring a different approach to connecting system power.

Auxiliary power connectors on the backplane are provided to help improve system Mean Time To Repair (MTTR). All power can be delivered to the SHB via the board's edge connectors. Core's PICMG 1.3 SHBs and backplane SHB edge connector slots have ample power pins available to meet the power demands of high-performance, performance-based processor SHBs like the Core CEP4. The ATX/EPS and +12V power connectors on the SEBP13-4/6/2 backplane also have an ample number of power pins available to meet these demands. The system designer needs to be aware of the potential power demands of the entire system including the particular SHB to ensure that both the power supply and the power connectors in the cable harness can safely deliver the necessary power to drive the entire system.

Specific implementations of ACPI signals, ATX/EPS power supply type and the operating system software will determine the specific connection method for the power supply. ACPI signal usage is optional and may be turned off using the SHBs BIOS and/or signal jumpers. Specific power connections and BIOS parameters will differ according to unique system design requirements.