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SEBP17-14/2 |
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17-slot PCI-Express/ PCI-X Backplane |
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FEATURES
• One SHB Express (PICMG 1.3) System Host Board Slot
• One x16 and one x8 PCI Express slot (mechanical)
• Two 64-bit/133MHz PCI-X Slots
• Twelve 64-bit/100MHz PCI-X Slots
• Four USB 2.0 backplane I/O connections
• Two 10/100/1000Base-T backplane Ethernet ports
• ATX, EPS and Extended-current power connection options
• Supports Core and PICMG 1.3 20-slot hole patterns
• Seamless support for PCI Express, PCI-X and universal PCI option cards |
SPECIFICATION
PCI Express slot one on the SEBP17-14/2 is a x16 slot that mechanically supports x16, x8, x4 and x1 PCI Express cards. PCI Express slot two is a x8 slot that mechanically supports x8, x4 and x1 PCI Express cards. PCI Express option card slot (PCE1) is driven directly by the SHB via a x4 PCI Express link between the card slot and the SHB slot. The actual speed of the PCI Express connection between the SHB and option card slot PCE1 depends on the SHB's PCI Express link configuration and the auto-negotiation/link training features of PCI Express. In order to use the second PCI Express slot (PCE2) a Core CE-00031 I/O expansion board must be used on Core's CEDX or CESX system host board. The CE-00031 provides a x4 PCI Express electrical connection to the PCE2 slot that enables communication between the SHB/IOB31 and the PCI Express option card.
Provides fourteen PCI Local Bus slots which support PCI-X and universal PCI option cards.
Accepts an SHB Express (PICMG® 1.3) compliant processor. Core's CEDX and CESX system host boards are examples of processors, SHBs or SBCs that are PCI Express compatible.
The PCI Express-to-Dual PCI-X bridges ease the transition to PCI Express by supporting the PCI Local Bus as well as enabling 64-bit PCI-X architectures capable of running at speeds up to 133MHz. The bridge chips are fully compliant with the PCI-X Addendum to the PCI Local Bus Specifications Revision 1.0 and the PCI Local Bus Specification 2.2.
The SHB Express specification defines optional I/O routings from the SHB to the backplane. Core's SEBP17-14/2 takes advantage of this new specification feature by providing two USB 2.0 headers capable of providing up to four USB 2.0 backplane ports.
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SPECIFICATION (CONT.)
POWER CONNECTORS
The backplane is available with an ATX or EPS power connector.
The EPS configuration is recommended for use with system host boards such as Core's CEDX that use dual, high-performance Intel® Xeon™ processors. Either the ATX or EPS configurations can be used with dual, low voltage Intel® Xeon™ processors or single processor configurations.
AUXILIARY POWER CONNECTOR
A +12V power connector is also provided for routing auxiliary power to the SHB's edge connectors. This new capability of PICMG 1.3 compliant SHBs and backplanes eliminates the need for auxiliary power connections on the system host board.
EXTENDED-CURRENT TERMINAL BLOCKS
Extended-current terminal blocks provide additional power capacity for power-intensive applications -- up to 80 Amps of +12V, 120 Amps of +3.3V and 80 Amps of +5V.
ETHERNET INTERFACES - 10/100/1000BASE-T
Core's SEBP17-14/2 backplane supports the optional Ethernet routing feature of the SHB Express specification. Two 10/100/1000Base-T Ethernet RJ-45 connectors are available for use on the backplane. Data communication performance of the backplane's Ethernet interfaces depends on the Ethernet controller hardware and configuration on the system host board. Consult your SHB Ethernet interface implementation method for details.
PRINTED CIRCUIT LAYERS
The backplane is an eight-layer, .062" thick board with three separate signal layers: +5V, +3.3V and ground. Multi-layer backplane construction provides excellent noise immunity.
POWER INDICATORS
The power indicators provide a convenient visual check for +5V, -5V, +5V AUX,+12V, -12V and +3.3V power connections. |
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Phone (858) 391-1006 Fax (858) 391-0109
© Copyright 2006-2008 Core Systems
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