SEBP6-3/2

GRAPHICS-CLASS PCI EXPRESS™ BACKPLANE
Core’s SEBP6-3/2 is a graphics-class backplane.  A graphics-class backplane provides a x16 PCI Express™ mechanical card slot that is driven with a x16 PCI Express electrical link. This backplane design feature enables x16 PCIe link support for high-end video and graphics cards by the graphics-class System Host Boards.

SHB SLOT 
Accepts an SHB Express™ (PICMG 1.3) compliant processor.  Core’s CEP4, CECD and MCG-series system host boards (SHBs) are examples of compliant PICMG 1.3 processors. The SEBP6-3/2 is optimized to fully utilize all available PCI Express links from graphics-class SHBs.

PCI EXPRESS SERIAL SLOTS
PCI Express option card slot PCIe1 on the SEBP6-3/2 can mechanically support x8, x4 and x1 PCI Express cards. The PCIe1 option card slot uses the PCIe link provided by the SHB via a Core IOB31 I/O expansion board.  The IOB31 when attached to a MCG-series SHB provides a x4 PCIe link from the SHB to the backplane’s PCIeS slot.  A CEP4 or CECD system host board may also be used and these SHBs will provide a x1 PCI Express link to the SEBP6-3/2 backplane’s PCIeS slot via an IOB31 module. 

PCIe3 is a x16 PCI Express mechanical slot that is driven by a x16 PCI Express link (A0) from the SHB. This slot is designed to electrically and mechanically support high-end PCI Express graphics and video cards that use a x16 PCI Express link to communicate to the system host board.

The actual speed of a PCI Express connection to an option card slot is determined by the SHB’s PCI Express link configuration and the auto-negotiation/link training features of PCI Express.

PCI-X/PCI PARALLEL BUS SLOTS
Three PCI-X slots (SLTA1 , SLTB1 and SLTB2 ) on the SEBP6-3/2 are connected to the SHB via a x4 PCI Express link (B0) via a PCI Express-to-PCI-X bridge chip. The bridge chip supports SLTA1 with a 64-bit/133MHz PCI-X interface and SLTB1 and SLTB2 with a 64-bit/100MHz PCI-X interface. These slots support PCI-X and universal PCI option cards, (i.e. 5V/3.3V combo or 3.3V only). The bridge chip will throttle-down the bus interface speed to match any card that has a speed capability less than the supported bus interface speed of a specific PCI-X backplane slot.

OPTIONAL USB 2.0 INTERFACES
The SHB Express specification defines optional I/O routings from the SHB to the backplane. Core’s SEBP6-3/2 takes advantage of this new specification feature by providing two USB 2.0 headers capable of providing up to four USB 2.0 backplane ports.

OPTIONAL ETHERNET INTERFACE
Core’s SEBP6-3/2 backplane supports the optional Ethernet routing feature of the SHB Express (PICMG 1.3) specification. One 10/100/1000Base-T Ethernet RJ-45 connector is available for use on the backplane. The SHB OPTIONAL BACKPLANE I/O SUPPORT TABLE explains the backplane I/O capabilities supported by Core’s PICMG 1.3 System Host Boards.   

POWER CONNECTORS
The standard SEBP6-3/2 backplane is available with a low-profile right-angle power connector suitable for use with either an ATX  or EPS power supply.  An optional SEBP6-3/2 is available with straight-in or vertical power connectors. Using straight-in power connectors may interfere with a full-length option card placed in the SLTB1 slot.

POWER INDICATORS
Surface-mount LEDs provide a convenient visual check for +5V,  -5V, +5V AUX,+12V, -12V and +3.3V power connection and status. CAUTION: Never install or remove the SHB or any option card from the SEBP6-3/2 backplane if the +5V AUX LED is GREEN.  If the system appears to be off and the+5V AUX LED is GREEN, you need to remove or turn off the incoming power to the system power supply.

AUXILIARY POWER CONNECTOR
The +12V power connector on the SEBP6-3/2 provides for routing auxiliary power to the SHB’s edge connectors.  This new capability of PICMG 1.3 compliant SHBs and backplanes eliminates the need for auxiliary power connections on the system host board.

PRINTED CIRCUIT LAYERS
The backplane is a six-layer, .062” thick board with three separate signal layers: +5V/+12V, +3.3V and ground. Multi-layer backplane construction provides excellent noise immunity.

CONNECTING POWER
A new approach is required to connect system power due to the combination of new power supply technologies and the soft-power control signals available via the Advanced Configuration and Power Interface (ACPI). ACPI signals are now supported by PICMG 1.3 SHBs and backplanes. Auxiliary power connectors located on the PICMG 1.3 backplanes now deliver all of the power directly to the edge connectors of the SHB.

Auxiliary power connectors on the backplane are provided to help improve system Mean Time To Repair (MTTR).  All power can be delivered to the SHB via the board’s edge connectors.  Core’s PICMG 1.3 SHBs and backplane SHB edge connector slots have ample power pins available to meet the power demands of high-performance dual-processor SHBs. The ATX/EPS and +12V power connectors on the SEBP6-3/2 backplane also have an ample number of power pins available to meet these demands. The system designer needs to be aware of the potential power demands of the entire system, including the particular SHB, to ensure that both the power supply and the power connectors in the cable harness can safely deliver the necessary power to drive the entire system.

Specific implementations of ACPI signals, ATX/EPS power supply type and the operating system software will determine the specific connection method for the power supply.

ACPI signal usage is optional and may be turned off using the SHB’s BIOS and/or signal jumpers. Specific power connections and BIOS parameters will differ depending on unique system design requirements. Refer to the Appendix B (Power Connection) and Advanced Setup BIOS sections found in the Technical Reference Manual for your specific Core system host board for more information.